NEO Semiconductor Achieves Breakthrough with 3D X-DRAM Proof-of-Concept for Next-Generation AI Memory

NEO Semiconductor, a recognized leader in advanced AI and memory technology, has announced successful proof-of-concept (POC) results for its innovative 3D X-DRAM technology. This achievement marks a significant step forward in the development of high-density memory solutions tailored for artificial intelligence and data-centric applications.

Strategic Investment and Industry Confidence

The company also revealed a new strategic investment led by Stan Shih, Founder and former Chairman and CEO of Acer, and a former Board Director of TSMC. Mr. Shih’s involvement underscores strong industry confidence in NEO Semiconductor’s vision and technological direction, supporting the company’s next phase of growth and innovation.

3D X-DRAM: Leveraging Existing 3D NAND Infrastructure

The POC test chips demonstrate that 3D X-DRAM can be manufactured using current 3D NAND infrastructure, including established equipment, materials, and cost-effective processes. With 3D NAND technology already surpassing 300 layers in commercial production, these results pave the way for next-generation, high-density 3D DRAM. The POC validates both the electrical performance and reliability of the new memory architecture.

Key Performance Metrics

  • Read/write latency: Less than 10 nanoseconds
  • Data retention: Over 1 second at 85°C (15 times better than the 64 ms JEDEC standard)
  • Bit-line disturbance: Over 1 second at 85°C
  • Word-line disturbance: Over 1 second at 85°C
  • Endurance: Greater than 1014 cycles

These results confirm a new scaling path for DRAM, enabling higher density, lower cost, and improved energy efficiency—key requirements for the AI era. By utilizing established 3D NAND manufacturing processes, NEO Semiconductor aims to accelerate the commercialization of 3D DRAM technology.

Industry Endorsement and Collaboration

Industry experts have highlighted the significance of this breakthrough. Jeongdong Choe, Senior Technical Fellow and SVP at TechInsights, noted that as traditional DRAM scaling approaches its physical limits, the industry is shifting toward 3D architectures and new cell technologies to meet the demands of AI and data-driven workloads. NEO Semiconductor’s silicon POC demonstrates real-world viability, aligning with the industry’s roadmap toward vertically scaled memory solutions.

This development is reminiscent of the transition to 3D NAND over the past decade, signaling the emergence of a new era for 3D DRAM beyond conventional scaling boundaries.

Academic and Industry Partnership

The proof-of-concept was developed in collaboration with National Yang Ming Chiao Tung University (NYCU) in Taiwan, specifically its Industry-Academia Innovation School (IAIS), and fabricated and tested at the National Institutes of Applied Research-Taiwan Semiconductor Research Institute (NIAR-TSRI). The device successfully passed rigorous electrical and reliability evaluations, confirming the robustness and stability of the proposed memory architecture.

Jack Sun, Senior Vice President of NYCU and Dean of IAIS, and former CTO of TSMC, emphasized the value of industry-academia partnerships in accelerating innovation from concept to practical implementation. The successful POC demonstrates the feasibility of advanced memory architectures using mature semiconductor processes.

Ongoing Development and Future Outlook

NEO Semiconductor’s recent funding, led by Stan Shih and other prominent technology investors, has supported the successful POC development and will drive the next phase of innovation. This includes array-level implementation, multi-layer test chip development, and deeper engagement with leading memory companies to explore strategic partnerships.

The company is actively collaborating with partners across the memory and semiconductor ecosystem to advance 3D X-DRAM technology toward commercialization. With validated POC results and growing industry engagement, NEO Semiconductor is positioned to make 3D X-DRAM a foundational technology for next-generation AI memory systems.

Upcoming Industry Presentation

Andy Hsu, CEO of NEO Semiconductor, will deliver a keynote presentation at the FMS: Future of Memory and Storage conference, where he will discuss the company’s 3D X-DRAM technology and share insights into the recent proof-of-concept results, including key performance and reliability metrics. The event will be held August 4-6, 2026, at the Santa Clara Convention Center in California, USA, where NEO Semiconductor will also be exhibiting.